1. Field of the Invention
The present invention generally relates to a flash memory cell transistor, and more specifically, to a flash memory cell transistor which compensates a difference in work function of pMOS and nMOS with a triple gate insulating film by using electron density trapped in a pMOS gate insulating film.
2. Description of the Prior Art
FIG. 1 is a cross-sectional diagram illustrating an example of a conventional flash memory cell transistor.
Referring to FIG. 1, a n-well 4 and a p-well 3 are formed on a silicon substrate 1, and an isolation oxide film 2 is formed between the n-well 4 and the p-well 3. The flash memory cell transistor of FIG. 1 that has a structure of a CMOS transistor comprises a nMOS region and a pMOS region. In the nMOS region, a nMOS ion-implantation region 5, a gate oxide film 7 and a n+ polysilicon gate electrode 8 are sequentially formed on the p-well 3. In the pMOS region, a pMOS ion-implantation region 6, a gate oxide film 7 and the n+ polysilicon gate electrode 8 are sequentially formed on the n-well 4.
Since n+ polysilicon is used as gate electrodes of the nMOS and the pMOS in the CMOS transistor of FIG. 1, a process for forming a gate electrode is simple.
However, as shown from FIG. 2a which represents an energy level of the nMOS region and FIG. 2b which represents an energy level of the pMOS region, the work function of the n+ polysilicon which is a gate electrode is the same because the p-well region of the nMOS region has a different Fermi level from that of the n-well region of the pMOS region.
Provided that the p-well and the n-well are doped with p-type impurities and n-type impurities of 1.0e17/cm3, respectively, a work function difference (ΦMS=ΦM−ΦSi) between a gate electrode and a semiconductor region is −0.98V in case of nMOS and −0.15V in case of pMOS.
In order to reduce the work function difference in the prior art of FIG. 1, p-type impurities that are the same as the p-well are ion-implanted in the nMOS channel ion-implantation region 5 while p-type impurities that are opposite to the n-well are ion-implanted in the pMOS ion-implantation region 6.
As the semiconductor technology has been improved, the channel length of nMOS and pMOS transistors becomes shorter and the thickness of a gate oxide film becomes thinner. As a result, an absolute value of a threshold voltage becomes smaller, and concentration of wells and channel ion-implantation becomes larger, so that a level of the threshold voltage is required to be maintained.
However, as shown in FIG. 1, ion-implantation impurities of the well are n-type but ion-implantation impurities of the channel region are p-type in case of pMOS. Therefore, as the concentration of the well becomes higher, that of the channel region is required to be also higher. As a result, it is difficult to fabricate a pMOS transistor in the prior art since the pMOS transistor having the channel length of less than 0.15 μm has a large short channel effect.
In order to solve the problem of the transistor in FIG. 1, the example of FIG. 3 where n+ polysilicon is used as a nMOS gate electrode and p+ polysilicon is used as a pMOS gate electrode has been disclosed.
In the transistor of FIG. 3, a n-well 4 and a p-well 3 are formed on a silicon substrate 1, and an isolation oxide film 2 is formed between the n-well 4 and the p-well 3. The flash memory cell transistor of FIG. 3 that has a structure of a CMOS transistor comprises a nMOS region and a pMOS region. In the nMOS region, a nMOS ion-implantation region 5, a gate oxide film 7 and a n+ polysilicon gate electrode 8 are sequentially formed on the p-well 3. In the pMOS region, a pMOS ion-implantation region 6, a gate oxide film 7 and a p+ ek silicon gate electrode 9 are sequentially formed on the n-well 4.
However, as shown from FIG. 4a which represents an energy level of the nMOS region and FIG. 4b which represents an energy level of the pMOS region, the work function of the n+ polysilicon in the nMOS region is 4.05 eV while that of the p+ polysilicon in the pMOS region is 5.15 eV.
Provided that the p-well and the n-well are doped with p-type impurities and n-type impurities of 1.0e17/cm3, respectively, a work function difference (ΦMS=ΦM−ΦSi) between a gate electrode and a semiconductor region is −0.97V in case of nMOS and +0.97V in case of pMOS, which are different in marks but the same in size. That is, the difference has a symmetrical structure since the threshold voltage of the nMOS is a positive value while that of the pMOS is a negative value.
In the transistor of FIG. 3, n+ polysilicon is used as a nMOS gate electrode, and p+ polysilicon is used as a pMOS gate electrode. P-type impurities which is the same as the p-well are ion-implanted in the nMOS channel ion-implantation region 5, and n-type impurities which is the same as the n-well are ion-implanted in the pMOS channel ion-implantation region 6. As a result, the short channel effect of the nMOS and the pMOS can be reduced in comparison with FIG. 1.
However, as the semiconductor technology has been improved, the thickness of the gate oxide film becomes thinner. As a result, the p-type impurities doped on the p+ polysilicon are diffused from the p+ polysilicon to the gate oxide film and the pMoS channel region during a subsequent thermal treatment process.
The p-type impurities diffused into the gate oxide film reduce reliability of the gate oxide film, and the p-type impurities diffused into the pMOS channel region through the gate oxide film change the value of the threshold voltage of the pMOS transistor.
Also, in a process for forming n+ and p+ polysilicon gates to the nMOS and the pMOS, respectively, inter-diffusion between the n+ polysilicon and the p+ polysilicon is required to be prevented in comparison with FIG. 1.
When the p+ polysilicon is used, the thickness of the gate oxide film becomes thinner due to insufficient doping of p-type impurities between the p+ polysilicon gate and the gate oxide film to increase poly depletion. As a result, the thickness of the effective gate oxide film becomes thicker and a current driving power is decreased.